The present invention relates to a system and method for defining semiconductor device layout parameters, and more particularly to a system for generating layers of semiconductor devices from a reduced set of specified layout parameters and layers by automatically determining the remaining non-specified layout parameters and layers.
Semiconductor circuits or “chips” have become widely used in nearly all machines and products that have electronic components. A typical electronic circuit design is initially conceived and tested schematically by a circuit design engineer, with a number of components and devices connected together to yield a circuit with desired performance characteristics. Once the circuit has been designed, it must be reconfigured from schematic form into a layout form. This is typically a job for a physical design engineer, working in concert with the circuit design engineer to create a graphic layout specifying a suitable semiconductor implementation of the circuit. The graphic layout of the device, which specifies all of the semiconductor device layout parameters, is then submitted to a foundry for fabrication of the chip.
Laying out an electronic circuit in a semiconductor implementation is a complicated task, and is governed by a large number of geometric rules. A layout of a semiconductor device contains geometric features such as polygons to indicate proper size, shape, location and separation of a certain circuit physical feature (a sub-component within a semiconductor device) from other physical features or to indicate proper isolation and separation among the circuit elements. Furthermore, the layout of a typical semiconductor device contains multiple drawing layers, each layer having one or more polygons. Generally, the more complicated the device is, the more layers and polygons the layout includes. Conventionally, the laying out of drawing layers and polygons contained therein, is done by the product company (the customer) even though most of the rules for layout are determined by the manufacturer. Verification of the layout, communication among the parties, and revision and updating of the rules make the complicated layout process even more complicated. It is therefore usually a very labor intensive project for a physical design engineer, and a single mistake in laying out any of the polygons of the device can render the entire chip inoperative. In a typical situation where a product company is a customer of a foundry, for example, device and process engineers of the foundry determine a set of layout rules while the circuit design and physical design engineers of the product company create the layout for a particular device based on the rules. The complete set of rules suitable for the device must be communicated to the engineers of the product company (the customer) by the foundry (manufacturer) and the layout done by the product company must be carefully checked by someone at the foundry to ensure that all rules have been correctly followed. In such a situation, not only is the use of the complete set of rules itself burdensome on the physical design engineers of the product company, communication and logistics involving two different companies or offices also add an extra layer of complexity.
It would therefore be an improvement in the art to provide a system for laying out semiconductor circuits that reduces the complexity for physical design engineers in creating layouts that will be submitted to a foundry for fabrication. Such a system is the subject of the present invention.